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VLSI Design Project

Syllabus and Overview

Overview for Part III Students making Option Choices

The following documents are available:

• 2025-2026

  • Individual Work

  • Group Work

    Full Chip Design Exercise 2026

    • Weather Station Specification 2026
      • Weather Sensor Assembly
      • AD7466 12-bit ADC datasheet

      • NHD-0108BZ-RN-YBW datasheet
      • ST7066U datasheet
        For reference: LCD User Manual - Although not for the this specific module, it includes examples relevant to the use of this sort of LCD display
      
      

    • Advanced Weather Station Specification 2026
      

      As above but with support for pressure and temperature and/or a 48x84 pixel L.C.D. Display and/or extra button(s).

      • MS5803-02BA Miniature Altimeter Module
      • PCD8544 datasheet

      • Pinout for advanced specification

    • Preparation for Handin

    • Simulation Environment
      • simulate
      • system
        • system.sv
        • lcd_char_display.sv
        • lcd_pixel_display.sv
        • weather.sv
        • wind_vane_adc.sv
        • pressure_sensor.sv
      • example
        • weather_core.sv
        • options.sv
        • monitor.sv
        • system.tcl
      • system2
        • storm1.sv

    • User's Guide & Technical Note Specification

    • Division of Labour Form

    • Individual Reflection and Evaluation Specification

    • Documentation Marking Scheme

  ---

  Provisional Timetable

  Tools and Techniques Phase
  Week 1	Lecture	Introduction
  	Lecture and Lab	ARM/RISC-V System-on-Chip
  Week 2	Lecture and Lab	RTL Synthesis using Synopsys Design Compiler
  		Timing Simulation
  Week 3	Lecture and Lab	Place and Route using Cadence Encounter
  Week 4	Lab	Verification and Sign-Off
  	Deliverable	Implementation of a Simple Design as a Complete IC	Individual Submission	20%
  Design and Implementation Phase
  Week 5	Deliverable	Design Proposal	Team Submissions	5%
  Week 6	Deliverable	Initial Behavioural Model		5%
  Week 7	Deliverable	Behavioural Model		5%
  Week 8	Deliverable	Gate-Level Design		5%
  Week 10	Deliverable	Full Chip Design		45%
  	Deliverable	User's Guide & Technical Note		10%
  Week 11	Lab	Demonstration
  	Deliverable	Individual Reflection	Individual Submission	5%

  
  ** Marks assignments above are likely to change as mini milestones (typically worth 1-3% each) are added to the schedule.

  ---

  Lecture Notes

  • Introduction

  • System on Chip design - ...unedited - ...AHB-Lite extra slides

  • Synthesis and Constraints

  • Introduction to Cadence Place and Route - ...unedited

  ---

  Tools and Techniques Phase

  As part of the tools and techniques phase, you will use RTL Synthesis, Place and Route and Post-Layout Simulation to implement and verify a simple design as a complete IC.

  • RTL Synthesis

    • Basel Halak's notes on RTL Synthesis using Design Compiler
      • Basic version including pads wrapper
        • Source files for Synthesis lab:
          • qmults.sv (qmults_stim.sv)
          • wrap_qmults.sv (wrap_qmults_stim.sv)
          • .synopsys_dc.setup
        • Constraints for wrap_qmults.sv
      • DFT version including pads wrapper and scan path insertion
        • Source files for Synthesis lab:
          • qmults.sv (qmults_stim.sv)
          • wrap_qmults.sv (wrap_qmults_stim.sv)
          • .synopsys_dc.setup
        • Constraints for wrap_qmults.sv

    • Reset Synchronization
      • reset_sync.sv

    • DFT Compiler Scan User Guide

    ▼► more synthesis notes

    • Basel Halak's notes on RTL Synthesis using Design Compiler
      • Required source files:
        • qmults.v
        • .synopsys_dc.setup

    • Basel Halak's notes on RTL Synthesis using Design Compiler (original version)

  • Place and Route

    • Place and Route using AMS 0.35um Libraries
      • Source files for place and route lab:
        • wrap_qmults.v
        • wrap_qmults.sdc
        • qmults_pads.txt
        • wrap_qmults.io

    • Add Peripheral Filler Cells (with 1.0 μm snap grid)
      • peri_fill.tcl

    ▼► more place and route notes

    • Full Chip Synthesis Demo
      • IO definition file used in this demo:
        • padring.txt
          - from which we can generate:
          • cpu.io
          • cpu.sv
      • Design files used in this demo:
        • src/ sub-directory contains SystemVerilog model files
          - note that this includes the cpu.sv file generated by process_pad_ring
        • files used to simulate this design:
          • system/ sub-directory contains SystemVerilog testbench files
          • simulate script runs the simulation
      • Required script files:
        • dc_script.tcl
        • demo_prepare_edi
        • edi_script.tcl
      Running the command init_ams_demo will copy the relevant files into ~/design/ams/ams_demo

    • Basel Halak's place and route notes

  • Post-Synthesis and Post-Layout Simulation

    • Digital Simulation using NC-Verilog - Lab Instructions

    • Basel Halak's digital simulation notes

    • Basel Halak's digital simulation lab notes

    • Additional information:
      • Post-synthesis simulation files should be in a directory named gate_level
      • Post-layout files should be in a directory named extracted

  • Post-Processing

    • Additional information:
      • Place Cadence Virtuoso layout files and exported GDS II file in a directory named post_process
      • To start Virtuoso use ams_cds -tech c35b4 -add ALL
      • Set process option to C35B4C3

  • ARM SoC Design

Background Lab Resources